---

clk

clock_source v11.0

Parameters clockFrequency 100000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

clk_50

clock_source v11.0

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cpu_0

altera_nios2 v11.0

Parameters userDefinedSettings tightlyCoupledInstructionMaster3MapParam tightlyCoupledInstructionMaster3AddrWidth 1 tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledDataMaster3MapParam tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster0AddrWidth 1 setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Dynamic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave cfi_flash_0.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _10 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false internalIrqMaskSystemInfo 511 instSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1A80000' end='0x1B00000' /><slave name='cpu_0.jtag_debug_module' start='0x1B01000' end='0x1B01800' /><slave name='epcs_controller.epcs_control_port' start='0x1B01800' end='0x1B02000' /></address-map> instAddrWidth 25 impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave sdram_0.s1 exceptionOffset 32 deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 deviceFamilyName Cyclone II debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _4 dcache_bursts false dataSlaveMapParam <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='VGA_0.avalon_slave_0' start='0x1800000' end='0x1A00000' /><slave name='sram_0.avalon_slave_0' start='0x1A80000' end='0x1B00000' /><slave name='cpu_0.jtag_debug_module' start='0x1B01000' end='0x1B01800' /><slave name='epcs_controller.epcs_control_port' start='0x1B01800' end='0x1B02000' /><slave name='uart_0.s1' start='0x1B02000' end='0x1B02020' /><slave name='timer_0.s1' start='0x1B02020' end='0x1B02040' /><slave name='timer_1.s1' start='0x1B02040' end='0x1B02060' /><slave name='lcd_16207_0.control_slave' start='0x1B02060' end='0x1B02070' /><slave name='led_red.s1' start='0x1B02070' end='0x1B02080' /><slave name='led_green.s1' start='0x1B02080' end='0x1B02090' /><slave name='button_pio.s1' start='0x1B02090' end='0x1B020A0' /><slave name='switch_pio.s1' start='0x1B020A0' end='0x1B020B0' /><slave name='SD_DAT.s1' start='0x1B020B0' end='0x1B020C0' /><slave name='SD_CMD.s1' start='0x1B020C0' end='0x1B020D0' /><slave name='SD_CLK.s1' start='0x1B020D0' end='0x1B020E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B020E0' end='0x1B020E8' /><slave name='DM9000A.avalon_slave_0' start='0x1B020E8' end='0x1B020F0' /><slave name='ISP1362.hc' start='0x1B020F0' end='0x1B020F8' /><slave name='ISP1362.dc' start='0x1B020F8' end='0x1B02100' /><slave name='Audio_0.avalon_slave_0' start='0x1B02100' end='0x1B02104' /><slave name='SEG7_Display.avalon_slave' start='0x1B02104' end='0x1B02108' /></address-map> dataAddrWidth 25 customInstSlavesSystemInfo <info/> cpuReset false cpuID 0 clockFrequency 100000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 100000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 4 DCACHE_LINE_SIZE_LOG2 2 DCACHE_SIZE 2048 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x800020 RESET_ADDR 0x1400000 BREAK_ADDR 0x1b01020 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 25 DATA_ADDR_WIDTH 25 NUM_OF_SHADOW_REG_SETS 0

---

tri_state_bridge_0

altera_avalon_tri_state_bridge v11.0

Parameters registerIncomingSignals true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cfi_flash_0

altera_avalon_cfi_flash v11.0

Parameters actualHoldTime 40.0 actualSetupTime 40.0 actualWaitTime 160.0 addressWidth 22 clockRate 100000000 corePreset CUSTOM dataWidth 8 holdTime 40 setupTime 40 sharedPorts s1/data,s1/address,s1/read_n timingUnits NS waitTime 160 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments SETUP_VALUE 40 WAIT_VALUE 160 HOLD_VALUE 40 TIMING_UNITS "ns" SIZE 4194304u

---

sdram_0

altera_avalon_new_sdram_controller v11.0

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 50000000 columnWidth 8 dataWidth 16 generateSimulationModel true initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 12 size 8388608 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 1 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 22 SDRAM_ROW_WIDTH 12 SDRAM_COL_WIDTH 8 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

---

epcs_controller

altera_avalon_epcs_flash_controller v11.0

Parameters autoSelectASMIAtom true deviceFamilyString Cyclone II useASMIAtom true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_OFFSET 512

---

jtag_uart_0

altera_avalon_jtag_uart v11.0

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

---

uart_0

altera_avalon_uart v11.0

Parameters baud 115200 baudError 0.01 clockRate 100000000 dataBits 8 fixedBaud true parity NONE simCharStream simInteractiveInputEnable false simInteractiveOutputEnable false simTrueBaud false stopBits 1 syncRegDepth 2 useCtsRts false useEopRegister false useRelativePathForSimFile false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BAUD 115200 DATA_BITS 8 FIXED_BAUD 1 PARITY 'N' STOP_BITS 1 SYNC_REG_DEPTH 2 USE_CTS_RTS 0 USE_EOP_REGISTER 0 SIM_TRUE_BAUD 0 SIM_CHAR_STREAM "" FREQ 100000000u

---

timer_0

altera_avalon_timer v11.0

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 100000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 100000000u LOAD_VALUE 99999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

timer_1

altera_avalon_timer v11.0

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 100000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 100000000u LOAD_VALUE 99999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

lcd_16207_0

altera_avalon_lcd_16207 v11.0

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

led_red

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 18 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 18 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

led_green

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 9 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 9 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

button_pio

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 100000000 direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "FALLING" IRQ_TYPE "EDGE" FREQ 100000000u

---

switch_pio

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 18 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 18 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

sram_0

sram_16bit_512k v1.0.2

Parameters AUTO_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

DM9000A

dm9000a v1.0.2

Parameters AUTO_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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VGA_0

binary_vga_controller v1.0.2

Parameters RAM_SIZE 307200 AUTO_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

Audio_0

audio_dac_fifo v1.0.2

Parameters REF_CLK 18432000 SAMPLE_RATE 48000 DATA_WIDTH 16 CHANNEL_NUM 2 AUTO_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

SD_DAT

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

SD_CMD

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

SD_CLK

altera_avalon_pio v11.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u

---

ISP1362

ISP1362_IF v1.0

Parameters AUTO_HC_CLOCK_CLOCK_RATE 100000000 AUTO_DC_CLOCK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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SEG7_Display

seg7_lut_8 v1.0.1

Parameters AUTO_CLK_CLOCK_RATE 100000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)