system_0 |

2012.02.21.15:53:38 | Datasheet

Overview

clk | system_0
clk_50
| uart_0
| rxd
| txd
| lcd_16207_0
| LCD_data
| LCD_E
| LCD_RS
| LCD_RW
| led_red
| out_port
| out_port
| in_port
| in_port
| bidir_port
| bidir_port
| out_port

Processor
cpu_0 Nios II 11.1
All Components
cpu_0 altera_nios2 11.1
tri_state_bridge_0 altera_avalon_tri_state_bridge 11.1
sdram_0 altera_avalon_new_sdram_controller 11.1
epcs_controller altera_avalon_epcs_flash_controller 11.1
jtag_uart_0 altera_avalon_jtag_uart 11.1
uart_0 altera_avalon_uart 11.1
timer_0 altera_avalon_timer 11.1
timer_1 altera_avalon_timer 11.1
lcd_16207_0 altera_avalon_lcd_16207 11.1
led_red altera_avalon_pio 11.1
led_green altera_avalon_pio 11.1
button_pio altera_avalon_pio 11.1
switch_pio altera_avalon_pio 11.1
SEG7_Display seg7_lut_8 1.0.1
sram_0 sram_16bit_512k 1.0.2
DM9000A dm9000a 1.0.2
VGA_0 binary_vga_controller 1.0.2
Audio_0 audio_dac_fifo 1.0.2
SD_DAT altera_avalon_pio 11.1
SD_CMD altera_avalon_pio 11.1
SD_CLK altera_avalon_pio 11.1
ISP1362 ISP1362_IF 1.0
Memory Map

| cpu_0
instruction_master | data_master
cpu_0 |  |
jtag_debug_module | 0x01b01800 | 0x01b01800
cfi_flash_0 |  |
s1 | 0x01400000 | 0x01400000
sdram_0 |  |
s1 | 0x00800000 | 0x00800000
epcs_controller |  |
epcs_control_port | 0x01b01000 | 0x01b01000
jtag_uart_0 |  |
avalon_jtag_slave |  | 0x01b020e0
uart_0 |  |
s1 |  | 0x01b02000
timer_0 |  |
s1 |  | 0x01b02020
timer_1 |  |
s1 |  | 0x01b02040
lcd_16207_0 |  |
control_slave |  | 0x01b02060
led_red |  |
s1 |  | 0x01b02070
led_green |  |
s1 |  | 0x01b02080
button_pio |  |
s1 |  | 0x01b02090
switch_pio |  |
s1 |  | 0x01b020a0
SEG7_Display |  |
avalon_slave |  | 0x01b02104
sram_0 |  |
avalon_slave_0 | 0x01a80000 | 0x01a80000
DM9000A |  |
avalon_slave_0 |  | 0x01b020e8
VGA_0 |  |
avalon_slave_0 |  | 0x01800000
Audio_0 |  |
avalon_slave_0 |  | 0x01b02100
SD_DAT |  |
s1 |  | 0x01b020b0
SD_CMD |  |
s1 |  | 0x01b020c0
SD_CLK |  |
s1 |  | 0x01b020d0
ISP1362 |  |
hc |  | 0x01b020f0
dc |  | 0x01b020f8

## clk

clock_source v11.1

## Parameters
clockFrequency | 100000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## clk_50

clock_source v11.1

## Parameters
clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## cpu_0

altera_nios2 v11.1

clk | clk | cpu_0
clk
|  | instruction_master | tri_state_bridge_0
|  | avalon_slave
|  | data_master
|  | avalon_slave
|  | instruction_master | sdram_0
|  | s1
|  | data_master
|  | s1
|  | instruction_master | epcs_controller
|  | epcs_control_port
|  | data_master
|  | epcs_control_port
|  | d_irq
|  | irq
|  | data_master | jtag_uart_0
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | uart_0
|  | s1
|  | d_irq
|  | irq
|  | data_master | timer_0
|  | s1
|  | d_irq
|  | irq
|  | data_master | timer_1
|  | s1
|  | d_irq
|  | irq
|  | data_master | lcd_16207_0
|  | control_slave
|  | data_master | led_red
|  | s1
|  | data_master | led_green
|  | s1
|  | data_master | button_pio
|  | s1
|  | d_irq
|  | irq
|  | data_master | switch_pio
|  | s1
|  | instruction_master | sram_0
|  | avalon_slave_0
|  | data_master
|  | avalon_slave_0
|  | data_master | DM9000A
|  | avalon_slave_0
|  | d_irq
|  | avalon_slave_0_irq
|  | data_master | VGA_0
|  | avalon_slave_0
|  | data_master | Audio_0
|  | avalon_slave_0
|  | data_master | SD_DAT
|  | s1
|  | data_master | SD_CMD
|  | s1
|  | data_master | SD_CLK
|  | s1
|  | data_master | SEG7_Display
|  | avalon_slave
|  | data_master | ISP1362
|  | hc
|  | d_irq
|  | hc_irq
|  | data_master
|  | dc
|  | d_irq
|  | dc_irq

## Parameters
userDefinedSettings |
tightlyCoupledInstructionMaster3MapParam |
tightlyCoupledInstructionMaster3AddrWidth | 1
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledDataMaster3MapParam |
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster0AddrWidth | 1
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Dynamic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | cfi_flash_0.s1
resetOffset | 0
muldiv_multiplierType | EmbeddedMulFast
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _10
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 511
instSlaveMapParam | <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='sram_0.avalon_slave_0' start='0x1A80000' end='0x1B00000' /><slave name='epcs_controller.epcs_control_port' start='0x1B01000' end='0x1B01800' /><slave name='cpu_0.jtag_debug_module' start='0x1B01800' end='0x1B02000' /></address-map>
instAddrWidth | 25
impl | Fast
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | sdram_0.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0
deviceFamilyName | Cyclone II
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _4
dcache_bursts | false
dataSlaveMapParam | <address-map><slave name='sdram_0.s1' start='0x800000' end='0x1000000' /><slave name='cfi_flash_0.s1' start='0x1400000' end='0x1800000' /><slave name='VGA_0.avalon_slave_0' start='0x1800000' end='0x1A00000' /><slave name='sram_0.avalon_slave_0' start='0x1A80000' end='0x1B00000' /><slave name='epcs_controller.epcs_control_port' start='0x1B01000' end='0x1B01800' /><slave name='cpu_0.jtag_debug_module' start='0x1B01800' end='0x1B02000' /><slave name='uart_0.s1' start='0x1B02000' end='0x1B02020' /><slave name='timer_0.s1' start='0x1B02020' end='0x1B02040' /><slave name='timer_1.s1' start='0x1B02040' end='0x1B02060' /><slave name='lcd_16207_0.control_slave' start='0x1B02060' end='0x1B02070' /><slave name='led_red.s1' start='0x1B02070' end='0x1B02080' /><slave name='led_green.s1' start='0x1B02080' end='0x1B02090' /><slave name='button_pio.s1' start='0x1B02090' end='0x1B020A0' /><slave name='switch_pio.s1' start='0x1B020A0' end='0x1B020B0' /><slave name='SD_DAT.s1' start='0x1B020B0' end='0x1B020C0' /><slave name='SD_CMD.s1' start='0x1B020C0' end='0x1B020D0' /><slave name='SD_CLK.s1' start='0x1B020D0' end='0x1B020E0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B020E0' end='0x1B020E8' /><slave name='DM9000A.avalon_slave_0' start='0x1B020E8' end='0x1B020F0' /><slave name='ISP1362.hc' start='0x1B020F0' end='0x1B020F8' /><slave name='ISP1362.dc' start='0x1B020F8' end='0x1B02100' /><slave name='Audio_0.avalon_slave_0' start='0x1B02100' end='0x1B02104' /><slave name='SEG7_Display.avalon_slave' start='0x1B02104' end='0x1B02108' /></address-map>
dataAddrWidth | 25
customInstSlavesSystemInfo | <info/>
cpuReset | false
cpuID | 0
clockFrequency | 100000000
breakSlave | cpu_0.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 100000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 4
DCACHE_LINE_SIZE_LOG2 | 2
DCACHE_SIZE | 2048
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x800020
RESET_ADDR | 0x1400000
BREAK_ADDR | 0x1b01820
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 0
INST_ADDR_WIDTH | 25
DATA_ADDR_WIDTH | 25
NUM_OF_SHADOW_REG_SETS | 0

## tri_state_bridge_0

altera_avalon_tri_state_bridge v11.1

clk | clk | tri_state_bridge_0
clk
cpu_0 | instruction_master
avalon_slave
data_master
avalon_slave
|  | tristate_master | cfi_flash_0
|  | s1

## Parameters
registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## cfi_flash_0

altera_avalon_cfi_flash v11.1

clk | clk | cfi_flash_0
clk
tri_state_bridge_0 | tristate_master
s1

## Parameters
actualHoldTime | 40.0
actualSetupTime | 40.0
actualWaitTime | 160.0
addressWidth | 22
clockRate | 100000000
corePreset | CUSTOM
dataWidth | 8
holdTime | 40
setupTime | 40
sharedPorts | s1/data,s1/address,s1/read_n
timingUnits | NS
waitTime | 160
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
SETUP_VALUE | 40
WAIT_VALUE | 160
HOLD_VALUE | 40
TIMING_UNITS | "ns"
SIZE | 4194304u

## sdram_0

altera_avalon_new_sdram_controller v11.1

cpu_0 | instruction_master | sdram_0
s1
data_master
s1
clk_50 | clk
clk

## Parameters
TAC | 5.5
TMRD | 3
TRCD | 20.0
TRFC | 70.0
TRP | 20.0
TWR | 14.0
casLatency | 3
clockRate | 50000000
columnWidth | 8
dataWidth | 16
generateSimulationModel | true
initNOPDelay | 0.0
initRefreshCommands | 2
masteredTristateBridgeSlave |
model | custom
numberOfBanks | 4
numberOfChipSelects | 1
pinsSharedViaTriState | false
powerUpDelay | 100.0
refreshPeriod | 15.625
registerDataIn | true
rowWidth | 12
size | 8388608
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
REGISTER_DATA_IN | 1
SIM_MODEL_BASE | 1
SDRAM_DATA_WIDTH | 16
SDRAM_ADDR_WIDTH | 22
SDRAM_ROW_WIDTH | 12
SDRAM_COL_WIDTH | 8
SDRAM_NUM_CHIPSELECTS | 1
SDRAM_NUM_BANKS | 4
REFRESH_PERIOD | 15.625
POWERUP_DELAY | 100.0
CAS_LATENCY | 3
T_RFC | 70.0
T_RP | 20.0
T_MRD | 3
T_RCD | 20.0
T_AC | 5.5
T_WR | 14.0
INIT_REFRESH_COMMANDS | 2
INIT_NOP_DELAY | 0.0
SHARED_DATA | 0
STARVATION_INDICATOR | 0
TRISTATE_BRIDGE_SLAVE | ""
IS_INITIALIZED | 1
SDRAM_BANK_WIDTH | 2
CONTENTS_INFO | ""

## epcs_controller

altera_avalon_epcs_flash_controller v11.1

clk | clk | epcs_controller
clk
cpu_0 | instruction_master
epcs_control_port
data_master
epcs_control_port
d_irq
irq

## Parameters
autoSelectASMIAtom | true
deviceFamilyString | Cyclone II
useASMIAtom | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
REGISTER_OFFSET | 512

## jtag_uart_0

altera_avalon_jtag_uart v11.1

clk | clk | jtag_uart_0
clk
cpu_0 | data_master
avalon_jtag_slave
d_irq
irq

## Parameters
allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 64
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 64
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
WRITE_DEPTH | 64
READ_DEPTH | 64
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## uart_0

altera_avalon_uart v11.1

clk | clk | uart_0
clk
cpu_0 | data_master
s1
d_irq
irq

## Parameters
baud | 115200
baudError | 0.01
clockRate | 100000000
dataBits | 8
fixedBaud | true
parity | NONE
simCharStream |
simInteractiveInputEnable | false
simInteractiveOutputEnable | false
simTrueBaud | false
stopBits | 1
syncRegDepth | 2
useCtsRts | false
useEopRegister | false
useRelativePathForSimFile | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
BAUD | 115200
DATA_BITS | 8
FIXED_BAUD | 1
PARITY | 'N'
STOP_BITS | 1
SYNC_REG_DEPTH | 2
USE_CTS_RTS | 0
USE_EOP_REGISTER | 0
SIM_TRUE_BAUD | 0
SIM_CHAR_STREAM | ""
FREQ | 100000000u

## timer_0

altera_avalon_timer v11.1

clk | clk | timer_0
clk
cpu_0 | data_master
s1
d_irq
irq

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## timer_1

altera_avalon_timer v11.1

clk | clk | timer_1
clk
cpu_0 | data_master
s1
d_irq
irq

## Parameters
alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 100000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 100000000u
LOAD_VALUE | 99999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## lcd_16207_0

altera_avalon_lcd_16207 v11.1

clk | clk | lcd_16207_0
clk
cpu_0 | data_master
control_slave

## Parameters
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## led_red

altera_avalon_pio v11.1

clk | clk | led_red
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## led_green

altera_avalon_pio v11.1

clk | clk | led_green
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 9
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 9
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## button_pio

altera_avalon_pio v11.1

clk | clk | button_pio
clk
cpu_0 | data_master
s1
d_irq
irq

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | true
clockRate | 100000000
direction | Input
edgeType | FALLING
generateIRQ | true
irqType | EDGE
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 1
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "FALLING"
IRQ_TYPE | "EDGE"
FREQ | 100000000u

## switch_pio

altera_avalon_pio v11.1

clk | clk | switch_pio
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## SEG7_Display

seg7_lut_8 v1.0.1

clk | clk | SEG7_Display
clk
cpu_0 | data_master
avalon_slave

## Parameters
AUTO_CLK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## sram_0

sram_16bit_512k v1.0.2

clk | clk | sram_0
clk
cpu_0 | instruction_master
avalon_slave_0
data_master
avalon_slave_0

## Parameters
AUTO_CLK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## DM9000A

dm9000a v1.0.2

clk | clk | DM9000A
clk
cpu_0 | data_master
avalon_slave_0
d_irq
avalon_slave_0_irq

## Parameters
AUTO_CLK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## VGA_0

binary_vga_controller v1.0.2

clk | clk | VGA_0
clk
cpu_0 | data_master
avalon_slave_0

## Parameters
RAM_SIZE | 307200
AUTO_CLK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## Audio_0

audio_dac_fifo v1.0.2

clk | clk | Audio_0
clk
cpu_0 | data_master
avalon_slave_0

## Parameters
REF_CLK | 18432000
SAMPLE_RATE | 48000
DATA_WIDTH | 16
CHANNEL_NUM | 2
AUTO_CLK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## SD_DAT

altera_avalon_pio v11.1

clk | clk | SD_DAT
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## SD_CMD

altera_avalon_pio v11.1

clk | clk | SD_CMD
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## SD_CLK

altera_avalon_pio v11.1

clk | clk | SD_CLK
clk
cpu_0 | data_master
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 100000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 1
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 1
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 100000000u

## ISP1362

ISP1362_IF v1.0

clk | clk | ISP1362
hc_clock
clk
dc_clock
cpu_0 | data_master
hc
d_irq
hc_irq
data_master
dc
d_irq
dc_irq

## Parameters
AUTO_HC_CLOCK_CLOCK_RATE | 100000000
AUTO_DC_CLOCK_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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